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Enhanced Synchronous Serial Interface (ESSI)
23
22
21
20
19
18
17
16
15
14
13
12
TS31
TS30
TS29
TS28
11
TS27
10
TS26
9
TS25
8
TS24
7
TS23
6
TS22
5
TS21
4
TS20
3
TS19
2
TS18
1
TS17
0
TS16
—Reserved bit; read as 0; write to 0 0 for future compatibility.
(ESSI0 X:$FFFFB3, ESSI1 X:$FFFFA3)
Figure 7-15. ESSI Transmit Slot Mask Register B (TSMB)
TSMA and TSMB (as in Figure 7-12 and Figure 7-13 ) can be seen as a single 32-bit register,
TSM. Bit n in TSM (TSn) is an enable/disable control bit for transmission in slot number N.
When TSn is cleared, all the data signals of the enabled transmitters are tri-stated during transmit
time slot number N. The data still transfers from the enabled transmit data register(s) to the
transmit shift register. However, the TDE and the TUE flags are not set. Consequently, during a
disabled slot, no transmitter empty interrupt is generated. The DSP is interrupted only for enabled
slots. Data written to the transmit data register when the transmitter empty interrupt request is
serviced transmits in the next enabled transmit time slot. When TSn is set, the transmit sequence
proceeds normally. Data transfers from the TX register to the shift register during slot number N,
and the TDE flag is set. The TSM slot mask does not conflict with the TSR. Even if a slot is
enabled in the TSM, you can chose to write to the TSR to tri-state the signals of the enabled
transmitters during the next transmission slot. Setting the bits in the TSM affects the next frame
transmission. The frame being transmitted is not affected by the new TSM setting. If the TSM is
read, it shows the current setting.
After a hardware RESET signal or software RESET instruction, the TSM register is reset to
$FFFFFFFF, enabling all 32 slots for data transmission.
DSP56311 User’s Manual, Rev. 2
7-32
Freescale Semiconductor
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